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Logoi - Rebel Technology

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Λόγοι is a voltage controlled clock divider, counter, and delay.

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months warranty
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Voltage controlled clock divider, counter, and delay.

Logoi is a voltage controlled clock divider, counter, and delay. It subdivides and adds time, creating organic, evolving signatures. Logoi brings movement and life to the trigger signal, from a subtle swing to bizarrely complex and intricate rhythms.

The functions of Logoi are split with division on the left, and addition on the right. The right side operates either in Counter mode, by adding clocks, or Shuffle mode, by adding a time delay. The mode is set by the centre switch.

The module has CV inputs and trigger outputs for each side, and a combined trigger output (centre bottom jack) which gives the output of both operations; divide and add.

The trigger input (bottom left and right jacks) is shared between division and addition. There is also a reset input (centre top) and manual reset switch (push switch up).

There are three LEDs indicating the divided and added output to the left and right, and the combined output in the centre.

The divider toggles its output every n clocks, where n is the divisor. The divisor is set with a manual (top knob) and CV level control, in a range from 1 to 32.

With the switch in the down position, the additive side functions as clock counter. The counter will output a trigger signal every m clocks, where m is the addend. The range is from 1 to 32 clocks, with 16 in the centre position.

The combined output will divide and count. If i is the incoming clock, n the divisor, and m the addend, then it will output a a trigger signal every i/n + m clocks.

Note that when the addend is larger than the divisor, in other words, n < m, then the divider frequency is higher than the addition and the combined output will never trigger.

With the switch in the centre position, the right side adds a time delay to the input. The amount of delay, or shuffle, ranges from 0ms to around 1000ms.

In shuffle mode, the combined output passes all clocks through until each time the divisor triggers, when it adds a time delay. The result is that every n-th clock is delayed by m, where m is the amount of shuffle and n is the divisor.

As in Count mode, if the divisor frequency is greater than the delay time, the combined output will not trigger. In shuffle mode, this is determined by the combination of input clock frequency and delay time.

Requires +5v

15 mA +12V
10 mA -12V
25 mA 5V
30 mm deep
Ø 3.90 (10 Votes) Average Rating
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